The design and fabrication technology of semiconductor memory devices has evolved rapidly over the past decade. In the case of dynamic random access memories (DRAMs), for example, the number of bits of data stored in a single DRAM chip has increased by a factor of four roughly every three years. This has resulted in the doubling of the size of memory systems at the same rate. Each new higher density generation of DRAMs reduces the number of individual memory chips needed in a system by one half. Fewer (but higher density) individual DRAM chips in memory systems results in fewer total number of pins available for transfer of data within the system. Reducing the number of pins available for receiving and transmitting information decreases the bandwidth of the memory system. That is, while internal to the memory chip large numbers of bits can be accessed per cycle, only a small percentage of the data can make it across the device boundary to the external world in any given time interval.
Today's advanced computing systems and microprocessors, however, demand greater and greater data bandwidths from memory systems. This has resulted in a more concerted effort in the memory industry to devise solutions to the bandwidth bottleneck. One approach to improving the data bandwidth in memory systems has focused on designing high speed interface structures. A memory sub-system based on a very fast and efficient interface technology that exploits a number of innovative data transmission techniques is described in U.S. Pat. No. 5,319,755 (Farmwald et al.) and U.S. Pat. No. 5,430,676 (Ware et al.). Other approaches have focused more on the internal circuitry of the memory devices to increase the rate of data transfer.